1. Technical Field
The present discussion relates to a nonvolatile memory electronic device and a method for manufacturing the same, and more particularly, to a nonvolatile memory electronic device including nanowire channel and nanoparticles-floating gate nodes and a method for manufacturing the same, in which the nonvolatile memory electronic device, which includes a semiconductor nanowire used as a charge transport channel and nanoparticles used as a charge trapping layer, is configured by allowing the nanoparticles to be adsorbed on a tunneling layer deposited on a surface of the semiconductor nanowire, such that charge carriers moving through the nanowire are tunneled to the nanoparticles by a program voltage applied to a gate, and then, the charge carriers are tunneled from the nanoparticles into the nanowire by an erase voltage applied to the gate, such that the nonvolatile memory electronic device can be operated at a low voltage and at high operation speed.
2. Related Art
A memory market based on DRAMs, which have led economic and industrial developments in the semiconductor field, facilitates various memory products, such as digital cameras, portable phones, and the like, due to developments in the mobile products industry and IT technology.
In the memory market, a flash memory market, which has recently experienced explosive demand, is rapidly growing every year and is expected to occupy most of the memory market in the future. In order to support the performance of IT products that have been developed recently, it is urgently needed to provide inexpensive next generation nonvolatile memory technology that can provide excellent storage capability and operation speeds, for supplementing the disadvantages of existing flash memories.
It is considered that such a technology will become a growth factor of economic and industrial development in the future, and it will be difficult to satisfy the demand required by the world if a development rate of such a technology is slowed down. In the case of nanowire-based floating gate memory devices, in which problems of existing flash memory structure are supplemented, it is reckoned that nanowire-based floating gate memory devices can be commercialized in the near future by employing an existing fabrication process. Therefore, research on nanowire-based floating gate memory devices should be made as soon as possible.
Existing flash memory devices have various problems when the size of cells are decreased, since the existing flash memory devices require a high operating voltage. Therefore, there is a limit to the extent that the size of existing flash memory can be decreased. In the case of existing flash memory devices, the program/erase voltage is higher than 10 volts, which is very high as compared with a CMOS driving voltage.
This is because electrons are injected to a floating gate by channel-hot-electrons (CHE) process, and the injected electrons are extracted again by high-field-assisted tunneling (Fowler-Nordheim tunneling) which requires a higher operating voltage compared with a operating voltage (3˜4 V) of direct tunneling.
Consequently, properties of a SiO2 thin film currently used as a tunneling layer are very important since an ultra-thin oxide film should be formed to enable the direct tunneling and reduce a program/erase time.
However, since many defects of the SiO2 thin film forming leakage paths make charge carriers difficult to be trapped in the floating gate nodes. In order to solve such a problem, it is on the rise as an important problem to eliminate defects of a tunneling layer.
In the meantime, although existing flash memory devices draws an attention as a mass storage media since the existing flash memory devices are excellent in degree of integration as compared with DRAM, it is imperative to develop an inexpensive next generation nonvolatile memory having superior information storage capability and fast operating speed even at a low voltage in order to support the performance of an IT apparatus that is developed very fast.
Furthermore, the size of memory cells should be reduced to increase the capacity of the flash memory devices, the thickness of a tunneling layer should be minimized in order to reduce the size of the cells, and the thinner tunneling layer enables lower program/erase voltage.
However, the existing flash memory devices have a program/erase voltage of about 9 to 12 V that is very higher than CMOS and DRAM driving volts. If several program/erase processes are performed at such a high voltage, a thin tunneling layer will be broken, creating a leakage path for charge carriers in the floating gate layer and causing the tunneling layer to lose its function.
Furthermore, a charge trapping layer of the existing flash memory devices is formed of a continuous thin film. However, when the tunneling layer is partially broken, a large leakage current is generated while charge carriers in the charge trapping layer flow into the channels through the damaged tunneling layer.
The existing devices further have the disadvantage of exhibiting poor endurance since the tunneling layer is considerably damaged as the program/erase processes are performed many times.
In order to prevent such a problem, thicker tunneling and insulating layers are required. However, there is a problem that the thicker tunneling and insulating layers deteriorate the degree of integration of a device and require a high program/erase voltage.